This invention relates to digital phase-locked loops. A phase-locked loop (PLL) is a device which is arranged to receive an input data signal and to produce an output clock signal having the same frequency and locked in phase to the input data. Such devices find application, for example, in data transmission systems or in magnetic recording.
One previously proposed digital PLL comprises a divide-by-n counter which is driven by an oscillator at n times the bit frequency of the input data, and produces one output clock pulse for each complete cycle of the counter. The clock signal is locked in phase to the incoming data by causing the data pulses to reset the counter to a predetermined state.
However, one problem with this form of PLL is that if the incoming data gets significantly out of phase with the clock signal (i.e. in the region of 180.degree. out of phase), the PLL may fail to operate correctly since it may not be able to decide whether the data is early or late with respect to the clock. One object of the present invention is to provide a novel digital PLL in which this problem is overcome.